The present invention relates to a circuit that can function as a reference voltage generator or can provide termination at the end of a transmission line, and uses a filter network to provide increased noise immunity.
In the art of digital systems, voltage dividers are used in many applications, such as generating a threshold voltage that is provided to one input of a differential receiver to detect a single-ended signal provided to the other input of the differential receiver, or providing termination at the end of a transmission line.
FIG. 1 shows a simple prior art voltage divider 10. Note that the term PFET will be used herein to reference a p-channel metal-oxide semiconductor field effect transistor (MOSFET). This type of transistors is also commonly known in the art as a PMOS transistor. Similarly, the term NFET will be used herein to reference an n-channel MOSFET. This type of transistors is also commonly known in the art as an NMOS transistor.
Voltage divider 10 comprises a PFET transistor 12 coupled between the voltage VDD, and the voltage divider output VOUT, and a NFET transistor 14 coupled between the voltage VSS and the voltage divider output VOUT. The gate terminal of PFET transistor 12 is coupled to VSS, and the gate terminal of NFET transistor 14 is coupled to VDD. The voltage present at the voltage divider output VOUT is halfway between the voltages of VDD and VSS.
One of the problems associated with the voltage divider configuration shown in FIG. 1 is noise. In FIG. 1, noise present in VSS will be amplified by PFET transistor 12 and appear on the output VOUT. Similarly, noise present in VDD will be amplified by NFET transistor 14 and appear on the output VOUT. Such noise is often present in digital systems, and when amplified by transistors 12 and 14, can degrade the performance of any circuit that depends on the reference voltage, such as a differential receiver or transmission line termination.
One prior art solution to this problem is to couple one or more capacitors between the voltage divider output and VSS, as is shown in FIG. 2. In FIG. 2, a voltage divider 16 comprises a PFET transistor 18 coupled between the voltage VDD, and the voltage divider output VOUT, and a NFET transistor 20 coupled between the voltage VSS and the voltage divider output VOUT. The gate terminal of PFET transistor 18 is coupled to VSS, and the gate terminal of NFET transistor 20 is coupled to VDD. Furthermore capacitor 24 is coupled between the voltage divider output VOUT and VSS. Unfortunately, to provide effective noise suppression for all circuits that require VOUT, especially in view of the amplification of noise produced by transistors 18 and 20, capacitor 24 must have a relatively large capacitance C. As is known in the art, large capacitances require a relatively large area on an integrated circuit, and therefore consume integrated circuit resources that could otherwise be used for other circuits.
The present invention is a voltage divider that suppresses noise in the voltage output by filtering the voltages at the gate terminals of the transistors that comprise the voltage divider. In a first embodiment of the present invention, a voltage divider includes a PFET transistor coupled between a voltage VDD and the voltage divider output, and an NFET transistor coupled between a voltage VSS and the voltage divider output. A resistor-capacitor (RC) filter is provided at each gate terminal of each of the transistors. Each RC filter is comprised or N RC stages, where N is equal to or greater than 1. For example, a four-stage RC filter coupled to the gate terminal of the PFET transistor comprises four resistors coupled in series between the gate terminal of the PFET transistor and the voltage VSS. At each of the nodes between the resistors, and at the node coupling the gate terminal of the PFET transistor to one of the resistors, a capacitor is coupled between the respective node and the voltage VDD. Similarly, a four-stage RC filter coupled to the gate terminal of the NFET transistor comprises four resistors coupled in series between the gate terminal of the NFET transistor and the voltage VDD. At each of the nodes between the resistors, and at the node coupling the NFET transistor to one of the resistors, a capacitor is coupled between the respective node and the voltage VSS.
In a second embodiment, the RC filter is fabricated using only transistors. One or more transistors having source and drain terminals coupled in series are used as resistors, and one or more transistors having source and drain terminals coupled together are used as capacitors, with the gate terminal serving as one terminal of the capacitor and the coupled source and drain terminals acting as another terminal of the capacitor. The transistors used as resistors also provide additional capacitance.
In both embodiments, noise present in VSS is eliminated at the gate terminal of the PFET transistor, and noise in VDD is eliminated at the gate terminal of the NFET transistor. Furthermore, noise present in VDD is applied to the source terminal of the PFET, and is also coupled to the gate terminal of the PFET by the capacitors, thereby keeping the source-to-gate voltage of the PFET constant and eliminating noise at the drain terminal of the PFET. Similarly, noise present in VSS is applied to the source terminal of the NFET, and is also coupled to the gate terminal of the NFET by the capacitors, thereby keeping the source-to-gate voltage of the NFET constant and eliminating noise at the drain terminal of the NFET. Since the present invention removes noise from the gate terminals of the transistors before the noise is amplified by the transistors, the resulting voltage divider output does not contain noise, and therefore a capacitor is not required between the output and VSS, as in the prior art. Since the filter is provided at the relatively high-impedance gate terminals of the NFET and PFET transistors, the capacitance values required in the RC filter can be relatively small. Accordingly, the present invention consumes a smaller area of the integrated circuit compared to prior art techniques. In addition, the present invention is easily extendable to past and future generations of MOS technology.